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Power Management
AV-51001
2013.12.26
Instead of using an external flash or ROM, you can configure the Arria V devices through PCIe using CvP.
The CvP mode offers the fastest configuration rate and flexibility with the easy-to-use PCIe hard IP block
interface. The Arria V CvP implementation conforms to the PCIe 100 ms power-up-to-active time require-
ment.
Note: Although Arria V GZ devices support PCIe Gen3, you can use only PCIe Gen1 and PCIe Gen2 for
CvP configuration scheme.
Related Information
Configuration via Protocol (CvP) Implementation in Altera FPGAs User Guide
Provides more information about CvP.
Power Management
Leveraging the FPGA architectural features, process technology advancements, and transceivers that are
designed for power efficiency, the Arria V devices consume less power than previous generation Arria FPGAs:
? Total device core power consumption — less by up to 50%.
? Transceiver channel power consumption — less by up to 50%.
Additionally, Arria V devices contain several hard IP blocks, including PCIe Gen1, Gen2, and Gen3, GbE,
SRIO, GPON, and CPRI protocols, that reduce logic resources and deliver substantial power savings of up
to 25% less power than equivalent soft implementations.
Altera Corporation
Arria V Device Overview
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